SRI VIDYA B.V; KIRANKUMAR.T. Delay optimized 16 X 16 bit Vedic Multiplier. Journal of Electronic Design Engineering, [S. l.], v. 3, n. 3, p. 8–12, 2017. Disponível em: https://www.matjournals.co.in/index.php/JOEDE/article/view/6766. Acesso em: 12 may. 2025.